When a device with a DRAM sub-system is powered up, a number of things happen before the DRAM gets to an operational state. The following state-machine from the JEDEC specification shows the various states the DRAM transitions through from power-up.
Figure 1: DDR4 State Machine
In essence, the initialization procedure consists of 4 distinct phases
Power-up and Initialization
Vref DQ Calibration
Read/Write Training (a.k.a Memory Training or Initial Calibration)
To better understand the following sections, let’s assume you have a system which looks like this – An ASIC/FPGA/Processor with 1 DIMM module.